1. Field of the Invention
The present invention relates to a logarithmic arithmetic unit, and more particularly, it relates to a logarithmic arithmetic unit carrying out logarithmic operations on floating-point data at a high speed.
2. Description of the Background Art
A logarithmic operation must be performed in order to position-control an industrial robot, and the logarithmic operation must be speeded up for operating the robot at a high speed. Japanese Patent Laying-Open No. 2-216583 (1990) proposes a method of executing a logarithmic operation by performing the following transformation on an exponent part xcex2 and a fixed-point part 2xcex1 of floating-point data Y thereby operating logY:
logY=log(2xcex1xc3x972xcex2) 
=xcex2xc3x97log2+log(xcfx86+xcex94xcfx86) 
≈xcex2xc3x97log2+logxcfx86+(xcex94xcfx86/xcfx86)xe2x88x92(xcex94xcfx86/xcfx86)2xe2x80x83xe2x80x83(1) 
where xcfx86 represents the high-order bit of the fixed-point part 2xcex1, and xcex94xcfx86 is expressed as (2xcex1xe2x88x92xcfx86). In the above expression (1), logxcfx86 is obtained through a logarithmic table with an address of the high-order bit of the fixed-point part 2xcex1, while the remaining terms are obtained by arithmetic operations.
According to the logarithmic operation method employing the expression (1), the division (xcex94xcfx86/xcfx86) must be performed. In order to calculate one digit of a result of division output in a binary number, the following processing (1) to (3) is generally performed:
(1) The dividend or a partial remainder is compared with the divisor.
(2) When the dividend or the partial remainder is greater than or equal to the divisor in the above item (1), 1 is set as a result bit while a value obtained by shifting a result of subtraction of the divisor from the dividend or the partial remainder one bit to the left is regarded as a new partial remainder.
(3) When the dividend or the partial remainder is less than the divisor in the above item (1), zero is set as a result bit while a value obtained by shifting the dividend or the partial remainder one bit; to the left is regarded as a new partial remainder.
While the result of division is sequentially obtained digit by digit by repeating the above processing (1) to (3), the division must be terminated on some digit. If the result of division is obtained up to an unnecessary digit, the processing is wasted and the processing time for the logarithmic operation is disadvantageously lengthened. Also when performing originally unnecessary division, the processing time for the logarithmic operation is disadvantageously lengthened.
Accordingly, an object of the present invention is to provide a logarithmic arithmetic unit and a logarithmic operation method performing a logarithmic operation at a high speed.
A logarithmic arithmetic unit according to an aspect of the present invention carries out logarithmic operations on floating-point data. The logarithmic arithmetic unit includes a first logarithmic operation part receiving an exponent part of the floating-point data for multiplying the exponent part by a prescribed value and obtaining the logarithm of 2 raised to the power specified by the exponent part, a logarithmic table memory storing a plurality of logarithmic values for receiving bit data expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data as an address and outputting a logarithmic value corresponding to the address, a divisional precision decision part receiving the exponent part of the floating-point data and deciding divisional precision on the basis of the exponent part, a division part connected to the divisional precision decision part for performing division on a dividend obtained by subtracting the bit data from the fixed-point part of the floating-point data and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision decided in the divisional precision decision part, a second logarithmic operation part connected to the division part for obtaining the logarithmic value of a value obtained by dividing the fixed-point part of the floating-point data by the bit data through the result of division in the division part and a sum operation part connected to the first logarithmic operation part, the logarithmic table memory and the second logarithmic operation part for adding outputs from the first logarithmic operation part, the logarithmic table memory and the second sum operation part to each other.
The arithmetic precision (divisional precision) of the division necessary for guaranteeing decided arithmetic precision of the logarithmic operation is recognizable from the exponent part of the floating-point data. Therefore, the division is performed to obtain the result up to the digit indicated by the divisional precision, so that the division may not be performed beyond necessity. Thus, the division is quickly terminated, so that the logarithmic operation can be performed at a high speed.
Preferably, the logarithmic arithmetic unit further includes a selection part connected to the divisional precision decision part and the second logarithmic operation part for selecting either zero or an operation value output from the second logarithmic operation part and supplying the selected value to the sum operation part in compliance with a selection control signal, and the divisional precision decision part generates a signal indicating whether or not to perform division on the basis of the exponent part and outputting the signal as the selection control signal.
When the divisional precision decision part determines that the result of division is zero, the selection part selects and outputs zero. The selection part outputs zero without waiting for the value output from the second logarithmic operation part. Therefore, the logarithmic operation can be executed at a higher speed.
More preferably, the logarithmic arithmetic unit further includes a determination circuit determining whether or not the value indicated by the exponent part is equal to a prescribed value and a selection part connected to the determination circuit and the first logarithmic operation part for selecting either zero or a value output from the first logarithmic operation part and supplying the selected value to the sum operation part in compliance with the result of determination of the determination circuit.
A value indicated by the exponent part when the value output from the first logarithmic operation part reaches zero is set as the prescribed value. Thus, the selection part can recognize whether or not the output from the first logarithmic operation part is zero by checking the result of determination of the determination circuit, for outputting zero without waiting for the output from the first logarithmic operation part when the output is zero. Thus, the logarithmic operation can be executed at a higher speed.
More preferably, the logarithmic arithmetic unit further includes a determination circuit determining whether or not the bit data is equal to a prescribed value and a selection part connected to the determination circuit and the logarithmic table memory for selecting either zero or a value output from the logarithmic table memory and supplying the selected value to the sum operation part in compliance with the result of determination of the determination circuit.
A value indicated by the bit data when the value output from the logarithmic table memory reaches zero is set as the prescribed value. Thus, the selection part can check whether or not the logarithmic value is zero by checking the result of determination of the determination circuit for outputting zero without waiting for the logarithmic value obtained by accessing the logarithmic table memory when the output from the logarithmic table memory is zero. Therefore, the logarithmic table memory may not store zero, leading to reduction of the memory capacity.
More preferably, the logarithmic arithmetic unit further includes a determination circuit determining whether or not bit data expressing a digit lower than a prescribed digit of the fixed-point part is equal to a prescribed value and a selection part connected to the determination circuit and the second logarithmic operation part for selecting either zero or a value output from the second logarithmic operation part and supplying the selected value to the sum operation part in compliance with the result of determination of the determination circuit.
A value indicated by the aforementioned bit data when the value output from the second logarithmic operation part reaches zero is set as the prescribed value. Thus, the selection part can check whether or not the output from the second logarithmic operation part is zero by checking the result of determination of the determination circuit, for outputting zero without waiting for the output from the second logarithmic operation part when the output is zero. Thus, the logarithmic operation can be executed at a high speed.
A logarithmic operation method according to another aspect of the present invention includes steps of obtaining a first value by multiplying an exponent part of floating-point data by a prescribed value, obtaining a second value serving as a logarithmic value for a value expressing a digit higher than a prescribed digit of a fixed-point part of the floating-point data, obtaining divisional precision on the basis of the exponent part, performing division on a dividend obtained by subtracting bit data expressing a digit higher than a prescribed digit of the fixed-point part of the floating-point data from the fixed-point part and a divisor of the bit data and obtaining a result of division of a number of digits set on the basis of the divisional precision, obtaining a third value serving as a logarithmic value of a value obtained by dividing the fixed-point part of the floating-point data by the bit data through the result of division and adding the first to third values to each other.
The arithmetic precision (divisional precision) of the division necessary for guaranteeing decided arithmetic precision of the logarithmic operation is recognizable from the exponent part of the floating-point data. Therefore, the division is performed to obtain the result up to the digit indicated by the divisional precision, so that the division may not be performed beyond necessity. Thus, the division is quickly terminated, so that the logarithmic operation can be performed at a high speed.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.